Embodiments of the present invention relate to a semiconductor device and a method for testing the same, and more specifically, to a technology for simultaneously screening an off-leakage-current fail caused by a passing gate effect and a neighbor gate effect.
In recent times, vertical-type cell transistors have been rapidly introduced to the market due to the increasing level of integration. However, in the case of using vertical-type cell transistors, capacitance between word lines is increased, resulting in a defective cell or failed cell operation. The number of defective or failed cells is rapidly increased with the increasing level of integration.
In a manufactured product of 100 nm or more that uses a cell transistor as a planar gate, a failed cell caused by an operation of a neighbor gate is not an issue. However, failed parts (also called a fail phenomenon) caused by the neighbor gate operation have been increasingly generated in the sub 100 nm technology that uses a recess gate.
Specifically, the fail phenomenon caused by the neighbor gate operation in the sub 100 nm technology that uses a recess gate has been detected in an actual wafer level test. The fail phenomenon is becoming severe as the level of integration continues to increase.
That is, after the development of 80 nm technology, a recess and a bulb-shaped gate have been used in an active region. Since a channel region is located below a junction region, cell function under a small critical dimension is unavoidably deteriorated due to the field influence caused by proximity with a neighbor passing gate or a neighbor gate. Such deterioration may immediately lead to a fail of the off-leakage current, so that serious quality problems such as a March Cache OFF and the like may occur in a packaging step and a modularizing step.
FIGS. 1A and 1B are conceptual diagrams illustrating a passing gate effect and a neighbor gate effect encountered in a conventional cell transistor.
In this case, the passing gate effect or the neighbor gate effect may indicate an exemplary phenomenon. That is, when a word line selected by an active command is enabled to a pumping voltage (VPP) level, a threshold voltage of a cell transistor corresponding to a turned-off neighbor word line is reduced.
FIG. 1A schematically shows the passing gate effect. The passing gate effect is as follows. That is, in the case of the passing gate effect, if the word line WL1 is enabled, a threshold voltage of a cell transistor of the word line WL0 corresponding to another neighbor active region is reduced.
FIG. 1B shows a neighbor gate effect. The neighbor gate effect is as follows. That is, in the case of the neighbor gate effect, if the word line WL1 is enabled, a threshold voltage of a cell transistor of the word line WL2 corresponding to the same active region is reduced.
In this way, if the threshold voltage of the cell transistor corresponding to a neighbor word line is lowered, an amount of an off-leakage current is increased, resulting in the occurrence of a defective cell.
In other words, the fail caused by the neighbor gate operation removes an “under margin” of a threshold voltage of the cell transistor, such that there arises a fail causing the off-leakage current. As tRAS time of the active region is increased, the possibility of a fail is also increased.
In this case, tRAS time indicates a specific time counted before a precharge operation is performed after the active operation. That is, the tRAS time is a predetermined time that is counted until a sufficient amount of charge is restored in a memory cell after the active operation.
In a memory product, a general active command can enable only one word line. The passing gate effect and the neighbor gate effect that are dependent upon a low margin of the cell threshold voltage are generated at a time at which the word line is enabled.
From the viewpoint of a test aspect, it is necessary to increase the tRAS time such that a sufficient time capable of screening the passing gate effect and the neighbor gate effect can be guaranteed.
However, if the tRAS time is controlled to be long without any plan, there arises an unexpected problem in a test time. That is, if a user attempts to screen all cells in a conventional memory product in which only one word line is enabled according to one active command, the test time is unnecessarily extended.
Therefore, there is needed a method for reducing a test time that screens the passing gate effect and the neighbor gate effect in a recess gate.
Meanwhile, FIG. 2 is a conceptual diagram illustrating a March-Cache-OFF fail encountered in a conventional module device.
Generally, as a representative method for testing a memory 3 such as a RAM in a Built In Self Test (BIST) circuit, a March-C algorithm can be used.
The March-C algorithm increases an address of the memory 3 simultaneously, writes a data value of ‘0’ in all addresses of the memory 3, again performs address increasing, reads the increased addresses, and reduces such addresses in such a manner that the foregoing operations are repeated. After that, using the data value ‘1’, the aforementioned operations are repeated. In this case, if the size of data is 2 bits or more, input data is configured in a combination pattern of two values ‘0’ and ‘1’, and a test for deciding the presence or absence of interference between data units assigned to the same address is performed. The above-mentioned phenomenon is referred to as a Data Back Ground function.
In order to test the memory 3 located on a board, the conventional method uses the BIST logic embedded in the memory 3 or uses a Central Processing Unit (CPU) 1. The chip Set 2 is connected between the CPU 1 and the memory 3, and performs address mapping.
The memory 3 includes a system region, a program region, and a test region. In this case, the program region stores information for carrying out a Cache-off test in the memory. During the execution of program, the program storing region is continuously accessed. A neighbor word line WL of the program region encounters a failure (also called a fail) of a specific address according to the increasing distant time.
The conventional device separately tests each of a passing gate screen item and a neighbor gate screen item using a quarter (¼) of the word line (WL) such that it can screen a low margin deterioration of the passing gate effect and the neighbor gate effect.
In this case, the pattern is prolonged, and the test time is also increased. In addition, the pattern detection capability is deteriorated so that direct fail of low margin deterioration occurs in a module, resulting in a March cache-off fail.
FIG. 3 is a timing diagram illustrating active and precharge operations of a conventional semiconductor device.
Referring to FIG. 3, the precharge command PCG allows the word line WL to be deactivated to a low level, and allows the sense amplifier SA to be turned off. In addition, the bit line precharge unit is activated to a high level during a normal activation time. Therefore, if data is set to ‘1’, the bit line BL is equalized to a level of a bit line precharge voltage VBLP in response to a bit line equalization signal BLEQ. In this case, the bit line precharge voltage (VBLP) level is set to about 0.7 V higher than a level of a ground voltage (VSS).
After that, if the bit line precharge unit is deactivated, the bit line equalization signal BLEQ is deactivated to a low level. In addition, if the word line WL is activated to a high level by an active command ACT, electric charges are distributed to bit lines. Thereafter, the sense amplifier SA is turned on and then normally operated.
If data stored in a cell is set to ‘1’, the bit line BL is increased to a level of a core voltage VCORE. The VCORE level is set to about 1.4 V higher than the precharge voltage VBLP level.